(1) Field of the Invention
The present invention relates to a semiconductor memory, in particular to a virtual ground memory array having redundant functions, made up of floating gate type non-volatile semiconductor memory cells.
(2) Description of the Related Art
In recent years, virtual ground type flash memory devices aiming for high packing density have drawn attention, such as for example, `A New Cell Structure for Sub-quarter Micron High Density Flash memory` (IEDM Technical Digest, pp.269-270, 1995), and an ACT (Asymmetrical Contactless Transistor) type flash memory disclosed in `An investigation of a sensing method of an ACT type flash memory` (ICD97-21, p37, 1997, Technical Report of the Institute of Electronics Information and Communication Engineers).
FIG. 1 is a sectional view showing the structure of an ACT type flash memory cell. In the memory cell (storage element) structure, a drain region 2 and source regions 3A and 3B are formed with n-type impurities over a p-type well 1 with a predetermined distance therebetween, while a control gate 4 for applying the gate voltage is formed across the gap between drain 2 and sources 3A and 3B. Control gate 4 is formed in layers with a control gate layer 5, an inter-layer insulating film 6, a floating gate 7 and a tunnel oxide film 8. This cell is featured such that the donor density directly below the floating gate 7 differs between the drain 2 side and the source 3 side.
In an ACT type flash memory, data write operations (to be referred to as program operations) and data erasing operations (to be referred to as erase operations) are implemented based on the FN tunnel effect, and it is expected to be used for data storage.
For an ACT type flash memory, it is important to enhance the speed of serial data reading and the speed of programming (verifying). For example, the array of a flash memory is configured of a NAND, AND or other types. These array configurations perform read, program (verify) and other operations on one word-line basis. That is, fast operations can be realized by determining the data by sensing the signals for one word line at the same time.
Since an ACT type flash memory has a virtual ground type array configuration as shown in FIG. 3, it is necessary to perform 4 cycle or 8 cycle read operations (one cell for four bits or one cell for eight bits) when taking into account the influences of read upon other memory cells. The method of reading based on this scheme will be described with reference to FIG. 3.
For simplicity, the drawing in FIG. 3 shows three word lines (row lines) WL0 to WL2 with nine bit lines (column lines) BL0 to BL8.
For example, when a four cycle read operation is performed, for reading cells M1 and M5, which are encircled in FIG. 3, upon the first cycle, the two adjacent bit lines containing the target cell are applied with 1(V) and 0(V), respectively, while two adjacent bit lines containing the cells which are not the reading targets are applied with 0(V)-0(V), 1(V)-1(V), or 0(V)-1(V). Thus, bit lines BL0 through BL8 are applied with voltages "1, 1, 0, 0, 1, 1, 0, 0, 1" (V: volt), in this order.
This reading technique enables reading free from influence upon other memory cells even with a virtual ground configuration.
One of the necessary techniques for such memory devices in order to improve the production yield is the redundancy method. Referring first to FIG. 4, bit-line failure in a conventional flash memory of a NOR type array will be described. Examples of failures are as follows:
X1: bit line open PA1 X2: Short-circuit between one bit line and source line (common source); PA1 X3: Short-circuit between bit lines; and PA1 X4: Short-circuit between one bit line and the substrate. PA1 X1: Bit line open PA1 X3: Short-circuit between bit lines PA1 X4: Short-circuit between one bit line and the substrate. PA1 a number of electrically programmable and erasable floating gate field effect transistors each having a control gate, a drain and a source, arranged matrix-wise in rows and columns forming an array, so that the control gates of the floating gate field effect transistors constituting each row are connected with one row line and the drains or sources of the floating gate field effect transistors constituting each column are connected with one column line, PA1 the method includes the steps of: PA1 when a defect occurs in a column line, PA1 using as the substitute memory, the floating gate field effect transistors for redundancy connected to redundancy column lines in a number as many as those of the floating gate field effect transistors of which the thresholds are set at the high state. PA1 a number of floating gate field effect transistors which each include a control gate having a control gate layer, an inter-layer insulating film and a floating gate, a drain and a source and are electrically programmable and erasable by injecting electrons into, or drawing electrons from, the floating gate by using the FN tunnel effect, and are arranged matrix-wise in rows and columns forming an array, so that the control gates of the floating gate field effect transistors constituting each row are connected with one row line and the drains or sources of the floating gate field effect transistors constituting each column are connected with one column line, PA1 the method includes the steps of: PA1 when a defect occurs in a column line, PA1 a non-volatile semiconductor memory having a virtual ground type array of a number of floating gate field effect transistors which each include a control gate having a control gate layer, an inter-layer insulating film and a floating gate, a drain and a source, are electrically programmable and erasable by injecting electrons into, or drawing electrons from, the floating gate by using the FN tunnel effect, and are arranged matrix-wise in rows and columns, wherein the control gates of the floating gate field effect transistors constituting each row are connected with one row line and the drains or sources of the floating gate field effect transistors constituting each column are connected with one column line; PA1 a memory for redundancy having the floating gate field effect transistors connected to one redundancy column line or lines in a number at least equal to the number of the rows of the array; PA1 a means for raising the threshold levels of the floating gate field effect transistors connected to one column line or more; and PA1 a means for enabling the floating gate field effect transistors connected to the redundancy column line or lines to be used for memory.
FIG. 4 shows part of a flash memory circuit for a conventional NOR type array configuration which has an unillustrated page buffer and performs programming on the word-line basis or for each word line WL1, 2 or 3 as a unit. Each bit line BL0-BL4 has a sense amplifier SA0-SA4. This circuit further includes a redundant array 9.
The read (verify) operation by this NOR type array configuration is found in `A 32 Mb AND type flash memory` (ICD95-39, p63 (1995), Technical Report of the Institute of Electronics Information and Communication Engineers).
First, all the bit lines BL are pre-charged and then one word line WL is set to a high level so that the signals are compared with the reference voltage to determine the data. That is, the data is latched by latch type sense amplifiers SA. The data is sequentially selected by the column decoder (designated at 10) to be output to an unillustrated output buffer.
When the data is latched by sense amplifiers SA in the NOR array type flash memory as stated above, if the array has defects such as X1, X2 and X4, only the single sense amplifier which is connected to one bit line produces erroneous data. More specifically, for the defect X1 or X2, sense amplifier SA0 connected to bit line BL0 produces erroneous data; for the defect X4, sense amplifier SA1 connected to bit line BL1 produces erroneous data.
For the defect X3 as compared to the above, sense amplifiers SA1 and SA2 connected to the two bit lines BL1 and BL2 produce erroneous data.
For the case where redundant bit lines are used for the array having the above defects X1 to X4, the data from redundant array 9 may and should be read out only when the sense amplifier SA latching the erroneous data is selected by column decoder 10 to transfer the data to an unillustrated buffer. In this case, the sensing of other memory cells will not have any influence from the memory cells connected to the defective bit line, regardless of the fact that their thresholds are either in the low or high state.
As has been described, in the conventional semiconductor memory redundancy method, redundant replacement was used for defective bit lines. The description of the prior art example in Japanese Patent Publication No.2,600,435 and the description in Japanese Patent Application Laid-Open Hei 7 No.230,700, disclose that a defective node (of word line and bit line) is replaced with only the defective bit line (its source line).
In a virtual ground type flash memory, however, it is not possible to correct the defective array by replacing only the defective node with the node connected to one redundant memory cell.
Now, the bit line failure in the virtual ground type flash memory will be described. The defects in this case are follows:
Referring to FIGS. 5A to 7, explanation will be made on the problems occurring when correction to bit line defects in the virtual ground type flash memory is attempted by the redundancy method which has been used for correcting the bit line failure of a conventional NOR type array.
FIG. 5A shows a memory array configuration with a defect, and FIG. 5B shows the influences upon the readout data from memory cells M0 to M3 (change in bit line voltage and the readout data pass-fail state) when the memory array has a bit-line open defect at X1.
Suppose that bit-line open defect occurs at X1 on bit line BL2 and the data is read out from the memory cells connected to word line WL0.
First, when the data in memory cell M0 is read out, the voltage to be applied to each bit line is as follows: 1 V is applied to bit lines BL0, BL3, BL4, BL7 and BL8 and 0V is applied to bit lines BL1, BL2, BL5 and BL6. FIG. 5B shows this state. It is assumed that the thresholds of memory cells M0, M1 and M2 are in the low state (not greater than 1(V)) as shown in FIG. 2. Since potential of bit line BL2 is floating, the line cannot be retained at 0 V. The voltage applied to bit line BL3, i.e., 1 V, is applied to bit line BL2 via memory cell M2 having a low threshold and also applied to bit line BL1 so that the voltage of bit line BL1 rises greater than the unaffected voltage, i.e., 0 V. As a result, memory cell M0 is misjudged as a cell having a high threshold.
When the data in memory cell M1 is read out, the voltage applied to each bit line is as shown in FIG. 5B. In this case, since bit line BL2 is floating, the line cannot be driven at 0 V so that the data cannot be read.
When the data from memory cell M2 is read out, the sense node (BL2) is floating as understood from the voltage applied to each bit line shown in FIG. 5B, so that the data cannot be read.
When data in memory cell M3 is read out, the voltage applied to each bit line is as shown in FIG. 5B. When memory cell M2 has a low threshold state while memory cell M3 from which data is read out has a high threshold state, bit line BL2 cannot be driven at 1 V. Further, a voltage is applied from bit line BL3 to memory cell M2 having a low threshold, resultantly the voltage of bit line BL3 lowers. Consequently, the threshold of memory cell M3 is misjudged as being at a low level due to the voltage drop of bit line BL3 , so that the data is misread.
As described above, in the case of a virtual ground type, only one bit line open causes the memory cells connected to the four bit lines to produce erroneous data. Therefore, the memory cells connected to the four bit lines need to be replaced.
Next, explanation will be made of a case where data is read out from memory cells connected to word line WL0 when a short-circuit (defect `X3`) occurs between bit lines BL3 and BL4 as shown in FIG. 6A. FIG. 6B shows the applied voltage state and readout data pass-fail state when each memory cell is read.
When the data from memory cell M0 is read out, this operation is unaffected since bit lines BL3 and BL4 are set at the same voltage, i.e., 1 V.
Secondly, when the data from memory cell M1 is read out, bit line BL3 is set at 0V and bit line BL4 is set at 1V. If it is assumed that the thresholds of the memory cells M1 and M2 are low, the potential of bit line BL3 rises since bit lines BL3 and BL4 are short-circuited. The potential of bit line BL2 also further raises, through memory cell M2 having a low threshold, more than the normal array state. As a result, the potential of bit line BL1 remains at the same level, so that memory cell M1 is misjudged as having a high threshold.
Next, when the data from memory cell M2 is read out, bit lines BL3 and BL4 are set at 0 V so that the data can be read out without any influence.
When the data from memory cell M3 is read out, since sense node (BL3) and the node (BL4) to which 0 V is applied are short-circuited the data cannot be read correctly.
When the data from memory cell M4 is read out, a case is considered where the thresholds of memory cells M2 and M3 are low and the threshold of memory cell M4 from which data is read is high. In this case, since sense node BL4 is short-circuited to bit line BL3 , lowering at the node of bit line BL3 (the potential at the node lowers compared to that in a normal array) directly affects and lowers the potential at sense node BL4, resultantly the threshold of memory cell M4 is misjudged as being low, producing erroneous readout.
When the data from memory cell M5 is read out, bit lines BL3 and BL4 are set at 0 V and 1 V, respectively. When the threshold of memory cell M4 is low and the threshold of memory cell M5 from which data is read is high, the potential of bit line BL4 lowers and the potential of the node of bit line BL5 lowers compared to that of a normal array since bit lines BL3 and BL4 are short-circuited. Resultantly the threshold of memory cell M5 is misjudged as being low, producing erroneous readout again, in this case.
Readout from memory cells M6 and M7 will not be affected by this reading method and hence can be performed normally.
Next, explanation will be made of a case where data is read out from memory cells connected to word line WL0 when a short-circuit (defect `X4`) occurs between bit line BL2 and the substrate as shown in FIG. 7A. FIG. 7B shows the applied voltage states and the readout data pass-fail state when each memory cell is read. In this case, there are two patterns which disable normal readout. One is the case where data is read from memory cell M2. In this case, since sense node (BL2) is short-circuited to the substrate, normal readout can not be performed.
The other case occurs when, upon the readout from memory cell M3, the threshold of memory cell M2 is low and the threshold of memory cell M3 from which data is read is high. In this case, since bit line BL2 and the substrate are short-circuited, the potential of bit line BL2 lowers, further reducing the potential of bit line BL3 via memory cell M3 having a low threshold. Resultantly, the cell is misjudged as being low, producing erroneous readout.
As has been described, when a defect occurs in bit lines in a virtual ground type flash memory, the defect affects the readout from memory cells which are not connected to the defective bit lines. Therefore, only having redundant replacement of the defective bit lines is not good enough, rather a number of bit lines need to be replaced.